OZ1KLK: VHDL Reference Guide

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(last edit: 24. september 2012)

Assert

A sequential or concurrent statement used to write out a message when an exception occurs.
If the condition is False, the simulator writes out a report to the screen or log file.
The simulator may be instructed to halt if the severity is above a particular level.

Syntax

  [Label:] assert Condition 
    [report StringExpression]
      [severity Expression];

Where

Placement

  PACKAGE Pack IS
    ... 
  END PACKAGE Pack;

  PACKAGE BODY Pack IS
    ... 
  END PACKAGE BODY Pack;

  Blk:BLOCK 
    ... 
  BEGIN 
    ... 
  END BLOCK Blk;

  ENTITY Ent IS
    ... 
  BEGIN 
    ... 
  END ENTITY Ent;

  ARCHITECTURE Arc OF Ent IS
    ... 
  BEGIN 
    ... 
  END ARCHITECTURE Arc;

  CONFIGURATION Conf OF Ent IS
    ... 
  END CONFIGURATION Conf;

  Proc:PROCESS(...) 
    ... 
  BEGIN 
    ... 
  END PROCESS Proc;

  PROCEDURE P(...) IS
    ... 
  BEGIN 
    ... 
  END PROCEDURE P;

  FUNCTION F(...) RETURN Tp IS
    ... 
  BEGIN
    ... 
  END FUNCTION F;

generate-begin--end See Sequential Statement

Rules

Sequential statements can be labelled in VHDL'93, but not in VHDL'87.
The severity Expression must be of type Severity_level, which has the values Note, Warning, Error, Failure.
The default severity is Error.

Things to remember

Check carefully the sense of the Condition. The message is written when the Condition is False!

Synthesis

Assertions do not represent hardware. Synthesis tools ignore them or give a warning.

Example

  assert not (Reset = '0' and Set = '0')
    report "R-S conflict"
      severity Failure;

  assert Outputs = ExpectedOutputs
    report "Outputs differ from expected response";